Texas Instruments /MSP432E411Y /LCD0 /MISCLR

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Interpret as MISCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCD_MISCLR_DONE)LCD_MISCLR_DONE 0 (LCD_MISCLR_RRASTRDONE)LCD_MISCLR_RRASTRDONE 0 (LCD_MISCLR_SYNCS)LCD_MISCLR_SYNCS 0 (LCD_MISCLR_ACBS)LCD_MISCLR_ACBS 0 (LCD_MISCLR_FIFOU)LCD_MISCLR_FIFOU 0 (LCD_MISCLR_PALLOAD)LCD_MISCLR_PALLOAD 0 (LCD_MISCLR_EOF0)LCD_MISCLR_EOF0 0 (LCD_MISCLR_EOF1)LCD_MISCLR_EOF1

Description

LCD Interrupt Status and Clear

Fields

LCD_MISCLR_DONE

Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Enabled Interrupt and Clear

LCD_MISCLR_RRASTRDONE

Raster Mode Frame Done interrupt

LCD_MISCLR_SYNCS

Frame Synchronization Lost Enabled Interrupt and Clear

LCD_MISCLR_ACBS

AC Bias Count Enabled Interrupt and Clear

LCD_MISCLR_FIFOU

DMA FIFO Underflow Enabled Interrupt and Clear

LCD_MISCLR_PALLOAD

DMA Palette Loaded Enabled Interrupt and Clear

LCD_MISCLR_EOF0

DMA End-of-Frame 0 Raw Interrupt and Clear

LCD_MISCLR_EOF1

DMA End-of-Frame 1 Enabled Interrupt and Clear

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